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M52347SP/FP
Sync Signal Processor
REJ03F0190-0200 Rev.2.00 Sep 14, 2006
Description
The M52347 automatically selects three types of synchronous signals containing separate sync (positive and negative polarities of 0.5 to 2.5 VP-P), composite sync (positive and negative polarities of 0.5 to 2.5 VP-P) and sync-on-video (sync negative polarity), and performs waveform shaping. The IC is optimum to synchronous signal processing for multi-scan type display monitor.
Features
* * * * * Low power consumption with supply voltage of 5 V Capable of obtaining output information on whether to input synchronous signal, and on polarity Output of clamp pulse Equipped with V TIME GATE SW that enables selecting whether or not VD portion pulse is output from pin 14/15. Equipped with CLAMP SW that enables switching the clamp pulse output position.
Application
Display monitor
Recommended Operating Condition
Supply voltage range: Rated supply voltage: VCC = 4.5 to 5.5 V VCC = 5 V
Block Diagram
CLAMP TIMING
20
V.POL.
19
H.POL.
18
CLAMP+ OUT
17
VCC
16
HD- OUT
15
HD+ OUT
14
VD+ OUT
13
V S/S OUT
12
V S/S IN
11
CLAMP GEN
EDGE SW
V.TIME GATE
V.SYNC SEP
LOGIC LOGIC SYNC SEP
1 2 3 4 5
H SHAPE
6
H DET
7
V SHAPE
8
V DET
9 10
H.STATE V.STATE CLAMP SW
GREEN IN
GND
COMP/H COMP/H IN DET
V IN
V DET V TIME GATE SW
Rev.2.00 Sep 14, 2006 page 1 of 16
M52347SP/FP
Pin Arrangement
M52347SP/FP H.STATE V.STATE CLAMP SW GREEN IN GND COMP/H IN COMP/H DET V IN V DET V TIME GATE SW 1 2 3 4 5 6 7 8 9 10 (Top view) Outline: PRDP0020BA-A (20P4B) [SP] PRSP0020DA-A (20P2N-A) [FP] 20 19 18 17 16 15 14 13 12 11 CLAMP TIMING V.POL. H.POL. CLAMP+ OUT VCC HD- OUT HD+ OUT VD+ OUT V S/S OUT V S/S IN
Rev.2.00 Sep 14, 2006 page 2 of 16
M52347SP/FP
Absolute Maximum Ratings
(Ta = 25C, unless otherwise noted)
Item Supply voltage Power dissipation Electrostatic discharge Operating temperature Storage temperature VCC Pd Surge Topr Tstg Symbol Ratings 6.0 1237.6 (SP), 827.8 (FP) 200 -20 to +85 -40 to +150 Unit V mW V C C
Electrical Characteristics
(Ta = 25C, VCC = 12 V, unless otherwise noted)
Item Circuit current Pin 1 output Hi level
TP In Limits Relay Condition Condition put 10 Pin Symbol Min. Typ. Max. Unit 4 6 8 16 3 ICC 40 53 66 mA 2 2 2 2 5 V 5 V 16
Input Condition
50 kHz 1 s 1 V P-P 50 kHz 1 s 1 V P-P 50 kHz 1 s 0.2 V P-P 50 kHz 1 s 1.0 V P-P 50 kHz 1 s 1 V P-P 50 kHz 1 s 1 V P-P 50 kHz 1 s 1.0 V P-P 50 kHz 1 s 0.2 V P-P 50 kHz 1 s 1 V P-P 50 kHz 1 s 1 V P-P 50 kHz 1 s 1 V P-P 50 kHz 1 s 1 V P-P 50 kHz 1 s 1 V P-P 50 kHz 1 s 1 V P-P 50 kHz 1 s 1 V P-P 50 kHz 1 s 1 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P
Output pin A 1
Output waveform DC
Note
1 OH
4.0
5.0
5.0
V
2
1
1
1
0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V
6 8 6 8 6 8 6 8 6 8 6 8 6 8 6 8 4 6 4 6
*1
Pin 1 output Low level
1 OL
0
0.04 0.5
V
2
1
1
1
1
DC
*1, *2
Pin 2 output Hi level
2 OH
4.0
5.0
5.0
V
2
1
1
1
2
DC
*1
Pin 2 output Low level
2 OL
0
0.04 0.5
V
2
1
1
1
2
DC
*1, *2
Pin 18 output Hi level
18 OH
4.0
5.0
5.0
V
2
1
1
1
18
DC
*1
Pin 18 output Low level
18 OL
0
0.04 0.5
V
2
1
1
1
18
DC
*1
Pin 19 output Hi level
19 OH
4.0
5.0
5.0
V
2
1
1
1
19
DC
*1
Pin 19 output Low level
19 OL
0
0.04 0.5
V
2
1
1
1
19
DC
*1
Pin 14 output Hi level
14 OH
4.0
5.0
5.0
V
1
1
2
1
14
V Meas
Pin 14 output Low level
14 OL
0
0.25 0.5
V
1
1
2
1
14 V Meas
Notes: 1. The true value table depends on Table 1 2. 0.2 VP-P of input signal is equivalent to NON SYNC.
Rev.2.00 Sep 14, 2006 page 3 of 16
M52347SP/FP
Electrical Characteristics (cont.)
Item Pin 15 output Hi level
TP In Limits Relay Condition Condition put Symbol Min. Typ. Max. Unit 4 6 8 16 3 10 Pin
Input Condition
50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 2 V P-P
Output pin 15
Output waveform
V Meas
Note
15 OH
4.0
5.0
5.0
V
1
1
2
1
0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V
4 6 4 6 4 6 4 6 8
Pin 15 output Low level
15 OL
0
0.25 0.5
V
1
1
2
1
15
V Meas
Pin 17 output Hi level
17 OH
4.0
5.0
5.0
V
1
1
2
1
17
V Meas
Pin 17 output Low level
17 OL
0
0.25 0.5
V
1
1
2
1
17
V Meas
Pin 13 output Hi level
13 OH
4.0
5.0
5.0
V
2
2
1
1
13
V Meas
Pin 13 output Low level
13 OL
0
0.25 0.5
V
2
2
1
1
8
50 kHz 1 s 2 V P-P
13
V Meas
Pin 12 output Hi level
12 OH
4.0
5.0
5.0
V
1
1
2
1
4 6 4 6 4
50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.05 V P-P
12
V Meas
Pin 12 output Low level
12 OL
0
0.25 0.5
V
1
1
2
1
12
V Meas
Sync-Sep Sync SS-NV input signal Max. noise amplitude voltage Sync-Sep Sync SS-LV input signal Min. amplitude voltage CLAMP SW V3H threshold voltage H CLAMP SW V3L threshold voltage H variable V TIME GATE SW threshold voltage variable V10
0.05 VP-P 1
2
2
1
14 15 17 14 17
No pulse must be output.
*3
0.2
VP-P
1
2
2
1
0V 5V 2.5 V 5V
4
50 kHz 1 s 0.2 V P-P
50 kHz No pulse must be output in this portion.
*4
2.8
3.1
3.4
V
2
1
2
1 Vari- 5 V
able
3 6
DC voltage must be applied. 50 kHz 1 s 2 V P-P DC voltage must be applied. 50 kHz 1 s 2 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 2 V P-P DC voltage must be applied.
14, 17 15 14, 17 15
*5
1.0
1.3
1.6
V
2
1
2
1 Vari- 5 V
able
3 6
*6
2.0
2.5
3.0
V
2
1
1
1
0 V Vari5 V able
6 8 10
*7 14 15
Notes: 3. Must not operate when input amplitude is 0.05 VP-P or less. (Pseudo noise signal) 4. Must operate when the input amplitude is 0.2 VP-P or more. 5. Checking output pulse for output with a voltage of 5 VDC applied, decrease the DC voltage and then measure the voltage when the output pulse is not output. 6. Checking output pulse for output with a voltage of 0 VDC applied, increase the DC voltage and then measure the voltage when the output pulse is not output. 7. Checking output pulse for output with a voltage of 5 VDC applied, decrease the DC voltage and then measure the voltage when the output pulse becomes narrow.
Rev.2.00 Sep 14, 2006 page 4 of 16
M52347SP/FP
Electrical Characteristics (cont.)
Item
TP In Limits Relay Condition Condition put Symbol Min. Typ. Max. Unit 4 6 8 16 3 10 Pin
Input Condition
50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 0.6 V P-P 50 kHz 1 s 2 V P-P 50 kHz 1 s 2 V P-P
Output pin 14
Output waveform
Input 6 (50%) Time Meas Output 14 (50%)
Note
HD+-delay time HD+-DA (A) HD+-delay time HD+-DB (B)
120 350
ns
1
1
2
1
0V 5V
5V
4 6
80
350
ns
1
1
2
1
0V 5V
5V
4 6 4 6
14
Input 6 (50%) Time Meas Output 14 (50%) Input 4 (50%) Time Meas Output 14 (50%)
HD+-delay time HD+-DC (C) HD+-delay time HD+-DD (D)
140 350
ns
1
1
2
1 2.5 V 5 V
14
120 350
ns
1
1
2
1 2.5 V 5 V
4 6
14
Input 4 (50%) Time Meas Output 14 (50%) Input 6 (50%) Time Meas Output 15 (50%)
HD--delay time HD--DA (A) HD--delay time HD--DB (B)
70
350
ns
1
1
2
1
0V 5V
5V
4 6
15
120 350
ns
1
1
2
1
0V 5V
5V
4 6 4 6
15
Input 6 (50%) Time Meas Output 15 (50%) Input 4 (50%) Time Meas Output 15 (50%)
HD--delay time HD--DC (C) HD--delay time HD--DD (D) CP+-delay time (A) CP+-DA
100 350
ns
1
1
2
1 2.5 V 5 V
15
150 350
ns
1
1
2
1 2.5 V 5 V
4 6
15
Input 4 (50%) Time Meas Output 15 (50%) Input 6 (50%) Time Meas
90
350
ns
1
1
2
1
0V
5V
4 6
17
Output 17 (50%)
CP+-delay time CP+-DB (B) CP+-delay time CP+-DC (C) CP+-PULSEWIDTH
130 350
ns
1
1
2
1 2.5 V 5 V
4 6
17
Input 4 (50%)
Time Meas
Output 17 (50%)
90
350
ns
1
1
2
1
5V
5V
4 6
17
Input 6 (50%) Time Meas Output 17 (50%) Time Meas Output 17 (50%)
CP+-PW 250 400 550
ns
1
1
2
1
0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V 2.5 V 5V 0V 5V
4 6 8
17
VD+-delay time VD+-DA (A) VD+-delay time VD+-DB (B)
100 350
ns
2
2
1
1
13
Input 8 (50%) Time Meas Output 13 (50%)
70
350
ns
2
2
1
1
8
50 kHz 1 s 2 V P-P
13
Input 8 (50%) Time Meas Output 13 (50%)
V Sync-Sep V11H threshold voltage H V Sync-Sep V11L threshold voltage L
3.0
3.5
4.0
V
2
1
2
1
0V
6 11
50 kHz 1 s 2 V P-P DC voltage must be applied. 50 kHz 1 s 2 V P-P DC voltage must be applied.
14 15 14 15
*8
1.3
1.8
2.3
V
2
1
2
1
0V 5V
0V
6 11
*9
Notes: 8. Checking output pulse for output with a voltage of 0 VDC applied, increase the DC voltage and then measure the voltage when the output pulse is not output. 9. Checking output pulse for output with a voltage of 5 VDC applied, decrease the DC voltage and then measure the voltage when the output pulse is output.
Rev.2.00 Sep 14, 2006 page 5 of 16
M52347SP/FP
Test Circuit
V11 100 p 43 k 12 V S/S OUT 13 VD+ OUT 14 HD+ OUT 15 HD- OUT 2 16 VCC 1 R16 75 k 17 CLAMP+ OUT GREEN IN 4 3.3 CLAMP SW 3 V3 TP19 4.3 k CLAMP 20 TIMING 220 p H.STATE 1 TP1 19 V.POL. V.STATE 2 TP2 1
R4
11 V S/S IN
V TIME 10 GATA SW V DET 9
V10
+
10
R8 2
TP13
V IN
8
4.7
1 TP14 COMP/H DET 7
+
0.0068
TP15
COMP/H IN
6
4.7
R6
2 1
A
5V 0.01 47 TP17
+
GND
5 2
TP18
18 H.POL.
:5V Units Resistance: Capacitance: F
Rev.2.00 Sep 14, 2006 page 6 of 16
M52347SP/FP
Pin Description
Pin No. 1 Name H.STATE DC Voltage (V) 0 VDC or 5 VDC Peripheral Circuit
20 k 1
Function Logic output pin for horizontal synchronous signal When pin 6 input signal is POSI, outputs "H"; when NON, outputs "L"; and when NEG, outputs "H". Logic output pin for vertical synchronous signal When pin 8 input signal is POSI, outputs "H"; when NON, outputs "L"; and when NEG, outputs "H". This SW is available to change the generating position of clamp pulse for input signal. (See Table 2.) VTH L = 0 to 1 V VTH M = 1.6 to 2.8 V VTH H = 3.4 to 5 V
2
V.STATE
0 VDC or 5 VDC
Same as pin 1
3
CLAMP SW
2.2 V when open
0.1 mA 3.1 V 1.3 V 22 k 20 k 20 k 28 k 3
4
GREEN IN
2.8 V when open
1 k 3.5 V
1 k 4
GREEN (SYNC ON VIDEO) input pin Input with negative sync. Comparison of pin 4 input signal and reference voltage within the IC performs synchronous separation. Grounding
5 6
GND COMP/H IN
2.5 V when open
20 k 1.5 k 1.5 k
20 k 6 10 k 2.8 V 10 k 2.5 V 0.3 mA 0.3 mA 10 k 2.2 V
Composite sync/H sync input pin. Bias is approx. 2.5 V and impedance is 10 k. The internal double threshold comparator is used for shaping waveform and detecting polarity. Optimum input amplitude is 0.6 VP-P at pin 6. Up to approx. 50% of duty, waveform shaping and polarity detection can be done. External capacitance is required as a filter pin for detecting polarity and detecting non-input. As the value is larger, the ripple is smaller and less malfunction occurs. However, this lowers the response speed of detection.
7
COMP/H DET
2.5 V when open (no signal)
12 k
12 k 75 k
7
2.5 V
2.8 V 20 k 20 k 2.2 V
8 9
V IN V DET
2.5 V when open 2.5 V when open (no signal)
Same as pin 6 Same as pin 7
V sync input pin Same as pin 6 Same as pin 7
Rev.2.00 Sep 14, 2006 page 7 of 16
M52347SP/FP
Pin Description (cont.)
Pin No. 10 Name V.TIME GATE SW DC Voltage (V) 3.2 V when open Peripheral Circuit Function V TIME GATE SW pin Can select whether to output the pulse of VD portion from pin 14, 15 output pulse. The threshold voltage is approx. 2.5 V. VTH L = 0 to 2 V VTH H = 3 to 5 V V S/S IN pin Inputs a signal of having externally integrated composite sync for V sync separation.
0.1 mA
2.5 V 30 k 20 k
10
11
V S/S IN
0.1 mA 7.5 k 4 k
11
1 k 5.5 k 1 k
20 k
1.75 k 0.2 mA 0.2 mA
12
V S/S OUT
1 k 12
V S/S pulse output pin No problem occurs when current of approx. 6 mA flows to internal part of the IC. To improve the rising speed, connect a resistance between power supplies. VD pulse output pin Same as pin 12 + HD pulse output pin Same as pin 12 HD- pulse output pin Same as pin 12 Power supply CLAMP pulse output pin Same as pin 12 Logic output pin for horizontal synchronous signal When pin 6 input signal is POSI, outputs "L"; when NON, outputs "L"; and when NEG, outputs "H". Logic output pin for vertical synchronous signal When pin 8 input signal is POSI, outputs "L"; when NON, outputs "L"; and when NEG, outputs "H". CLAMP TIMING pin The clamp pulse width is determined depending on the external resistance and capacitance. As the resistance value and capacitance value are larger, the clamp pulse width is wider.
+ +
13 14 15 16 17 18
VD OUT HD OUT HD-OUT VCC CLAMP OUT H.POL.
+ +
+
5V 0 VDC or 5 VDC
Same as pin 12 Same as pin 12 Same as pin 12 Same as pin 12 Same as pin 1
19
V.POL.
0 VDC or 5 VDC
Same as pin 1
20
CLAMP TIMING
3.0 V
4 k
4 k
1.9 V
3V 20 0.4 mA 0.2 mA
1.9 V
Rev.2.00 Sep 14, 2006 page 8 of 16
M52347SP/FP Table 1 Decorder Logic Output
Pin 8 Input V NON POSI. NEG. NON POSI. NEG. NON POSI. NEG. Output Pin 1 H H H H H H L L L 2 L H H L H H L H H 18 L L L H H H L L L 19 L L H L L H L L H
Pin 6 Input COMP/H POSI.
NEG.
NON.
Table 2
Clamp Pulse Position
Input Signal Pin 4 Pin 6 Pin 3 "H" 4 trailing edge 6 leading edge 6 leading edge Pin 17 Output Signal Pin 3 "M" 4 trailing edge 4 trailing edge Pin 3 "L" 4 trailing edge 6 trailing edge 6 trailing edge
Table 3
Output Priority Order
Output Signal Input Signal Pin 3 "H" "L" Pin 8 Pins 12, 14, 15, 17 4 6 4 6 6 6 Pin 13 11 11 8 8 11 8 8 Pin 3 "M" Pins 12, 14, 15, 17 4 4 4 4 Pin 13 11 11 8 8 8 8
Pin 4
Pin 6
Table 4
Allowable Input Amplitude Voltage
Pin 4 input amplitude
VV 0 to 2.1 (VP-P) fH = 10 Hz to 200 kHz VS 0.2 to 0.6 (VP-P) f = 10 Hz to 200 Hz V
Pin 6 input amplitude
VS 0.5 to 2.5 (VP-P) fH = 10 Hz to 200 kHz
Pin 8 input amplitude
VS 0.5 to 2.5 (VP-P) fV = 10 Hz to 200 Hz
Rev.2.00 Sep 14, 2006 page 9 of 16
M52347SP/FP
Application Method
1. Input Block 1) GREEN (SYNC ON VIDEO) IN (Pin 4) Input with sync negative polarity. Comparison of pin 4 input signal and the reference voltage of the inside of the IC performs the synchronous separation. When the input at pin 4 is less than or equal to the reference voltage (2.8 V) and the flowing current is more than or equal to the input sensitivity current (200 A or more), the signal is separated. When only a synchronous signal is input into pin 4, the operatable amplitude and the duty are as shown in Figure 1. If the IC does not operate normally with the video signal input, change the value of external resistance R to make the current optimum. But, when capacity value is too big, output response becomes bad. 2) COMP/H IN, VIN (pins 6 and 8) The composite sync input is connected to pin 6. H and V of the separate sync input are connected to pins 6 and 8, respectively. For each of pins 6 and 8, the bias is 2.5 V and the impedance is 10 k. The internal double threshold converter is used for shaping waveform and for detecting polarity. Average DC voltage of input signal is 2.5 V. Each threshold voltage is set at a voltage 0.3 V away from this voltage. If the duty ratio at pin 6 is small as shown in Figure 2, the optimum value is approx. 0.3 VP-P. If the duty ratio is large, the optimum value is approx. 0.6 VP-P. Figure 3 shows the allowable input amplitude and the reference value of duty test. Only 5 V TTL input, decrease the amplitude by resistor splitting. In addition, Figure 4 shows an example for improving the capability of the allowable duty when the input amplitude is 0.7 VP-P or more. To use the IC out of the standard value, remove the filter from pins 7 and 9, observe the waveform and check for a match with the waveform shown in Figure 5.
30
Operatable Maximum Duty (%)
25 20 15 10 5 0 0 0.2 0.4 f = 100 kHz
R = 56 k
R = 75 k 3.3 R
4
0.6
0.8
1.0
Input Amplitude (VP-P)
Figure 1
2.8 V 2.5 V 2.2 V Small POSI Duty Large NEG Duty
Figure 2
Rev.2.00 Sep 14, 2006 page 10 of 16
M52347SP/FP
50
Operatable Maximum Duty (%)
40
30
20
10
0 0 0.5 1 1.5 2 2.5
Input Amplitude (VP-P)
Figure 3
18 k Input signal 100 3 k This additional circuit (limiter) limits the amplitude to 0.6 VP-P. pin 6 or pin 8
:5V
Figure 4
4.5 V NEG input 2.5 V 2.5 V POSI input 0.5 V
Figure 5
Rev.2.00 Sep 14, 2006 page 11 of 16
M52347SP/FP 3) Polarity detection and non-input detection (pins 7 and 8) External capacitance is required as a filter pin to detect polarity and non-input. As the value is larger, the ripple is smaller and less malfunction occurs. However, the response speed for detection is lower. A sufficient external capacitance is 0.05 F with input of 15 kHz and 10 F with input of 60 kHz. However, check the frequency of the input signal in use and the filter pin waveform with the duty ratio conditions, and then check that the value is 3.1 V or more (2.8 V in capability) with positive polarity input and 1.9 V or less (2.2 V in capability) with negative polarity input. 4) V S/S IN (pin 11) Input a signal of having externally integrated composite sync for V sync separation. Composite sync input into pin 6 is output to pin 12. Output at 12 is externally integrated and is input into pin 11 for V sync separation. With the waveform at pin 11, check that the H element has been fully dropped. The threshold levels of sync separation, given hysteresis, are 3.5 V and 1.8 V.
Input waveform at pin 6 Waveform at pin 11 Output waveform at pin 13
VTH = 3.5 V VTH = 1.8 V
2. Clamp Pulse 1) Clamp pulse width CLAMP TIMING (Pin 20) The clamp pulse width is determined by the external resistance and the capacitance. As the resistance value and capacitance value are larger, the clamp pulse width is wider. The time constant is determined by the current flowing out of pin 20 and the capacitance value of the timing pin. The flow current at pin 20 is determined by the pin voltage and external resistance value. When the external resistance is 4.3 (that is 700 A) and the external capacitance is 220 pF, the pulse width is 0.4 s. 2) Clamp pulse position CLAMP SW (pin 3) When pin 3 is "M" or "L", fixing a higher-priority signal to the trailing edge results in occurrence of a clamp pulse. When pin 3 is "H", and only GREEN is input, clamp pulse occurs at the trailing edge. A clamp pulse also occurs at the leading edge when COMP/H only is input or when both COMP/H and GREEN are input.
8 7
Clamp Pulse Width (s)
6 5 4 R = 10 k 3 2 1 0 10 100 R = 4.3 k
1000
10000
Clamp Timing Capacitance at Pin 20 (pF)
Rev.2.00 Sep 14, 2006 page 12 of 16
M52347SP/FP 3. Sampling Pulse from VD Portion V TIME GATE SW (Pin 10) Whether to output the pulse of VD portion from pins 14 and 15 can be selected. When pin 10 is "H" or OPEN, pulse of the VD portion is output. When pin 10 is "L", the pulse of the VD portion is not output.
Output at pin 14 when pin 10 is "H" or OPEN
VD portion
Output at pin 14 when pin 10 is "L" Output at pin 15 when pin 10 is "H" or OPEN
VD portion
Output at pin 15 when pin 10 is "L"
4. Output Stage 1) Logic output (pins 1, 2, 18 and 19) The output format is as shown in the diagram below. When the internal load resistance of the IC is 20 k, a current of approx. 3 mA flows to the inside of the IC, no problem will occur.
20 k
2) Pulse output (pins 12, 13, 14, 15 and 17) The output format is as shown in the diagram below. When the internal load resistance of the IC is 1 k, a current of approx. 6 mA flows to the inside of the IC, no problem will occur. To improve the rising speed, connect a resistance between power supplies. Note that the low level of the output pulse goes up.
1k k
Rev.2.00 Sep 14, 2006 page 13 of 16
M52347SP/FP
0.8
Output Low Level (V)
0.6
0.4
0.2
0 0 2 4 6 8 10
External Resistance (k)
Typical Characteristics
Thermal Derating (Maximum Rating)
1400
Power Dissipation Pd (mW)
1237.6
1200 1000
827.8
SP FP 643.6
800 600 400 200 430.5
-25
0
0
25
50
75 85 100 125 150
Ambient Temperature Ta (C)
Rev.2.00 Sep 14, 2006 page 14 of 16
M52347SP/FP
Application Example (fH = 50 kHz, fV = 80 Hz)
(POSI NON NEG) (POSI NON NEG) VCC 5 V 220 p CLAMP TIMING 20 0.01 + H.POL. CLAMP+ OUT 18 17 47 HD- HD+ OUT OUT 16 15 14 VD+ OUT 13 V S/S OUT 12 43 k V S/S IN 11 100 p
4.3 k V.POL. 19
CLAMP GEN
EDGE SW
V.TIME GATE
V.SYNC SEP
LOGIC LOGIC SYNC SEP H SHAPE H DET V SHAPE V DET
1 H.STATE (POSI NON NEG) (POSI NON NEG)
2 V.STATE
3 CLAMP SW H M L 56 k
4 1.0 18 k
5 GND
6 4.7
7 8 COMP/H + 4.7 DET 0.068
9 V DET +
10 V TIME GATE SW H L
4.7 18 k
0.01
10
4.7
0.01
100 3k COMP/H IN
3k
100
:5V Units Resistance: Capacitance: F
GREEN IN
V IN
Note:
External circuit for input of pins 6 and 8 When amplitude of up to 5 VP-P is entered into this circuit, can be kept constant at approx. 0.6 VP-P. When the duty of input signal at pins 6 and 8 changes, the most broad support range is obtained with amplitude of 0.6 VP-P.
Rev.2.00 Sep 14, 2006 page 15 of 16
M52347SP/FP
Package Dimensions
JEITA Package Code P-SDIP20-6.3x19-1.78 RENESAS Code PRDP0020BA-A Previous Code 20P4B MASS[Typ.] 1.0g
20
11
1
10
*1
c
e1
E
*2 D
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
A
A2
Reference Symbol
Dimension in Millimeters
e SEATING PLANE
*3 b 3
bp
e1 D E A A1 A2 bp b3 c e L
Min Nom Max 7.32 7.62 7.92 18.8 19.0 19.2 6.15 6.3 6.45 4.5 0.51 3.3 0.38 0.48 0.58 0.9 1.0 1.3 0.22 0.27 0.34 0 15 1.528 1.778 2.028 3.0
JEITA Package Code P-SOP20-5.3x12.6-1.27
L
RENESAS Code PRSP0020DA-A
Previous Code 20P2N-A
MASS[Typ.] 0.3g
20 11
HE
*1
E
A1
F
1 Index mark
10
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
c
*2 D
A2
A1
Reference Symbol
Dimension in Millimeters
*3 e bp y Detail F
D E A2 A1 A bp c HE e y L
Min Nom Max 12.5 12.6 12.7 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0 8 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8
A
Rev.2.00 Sep 14, 2006 page 16 of 16
L
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Keep safety first in your circuit designs!
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